In semiconductor fabrication, various layers of dielectric insulating materials and etch stop layers are formed to produce a multi-level wiring structure in an integrated circuit semiconductor device. One of the limiting factors in the continuing evolution toward smaller device size and higher density has been signal delay caused by parasitic capacitance effects of dielectric insulating layers also referred to as inter-metal dielectric (IMD) layers as well as etch stop layers. For example, in reducing the capacitance contribution of IMD layers, a common approach for is to form the IMD layer of organic or porous inorganic silicon oxide based materials to reduce a dielectric constant.
As the dielectric constant of IMD layers has been reduced, particularly through the use of porous inorganic silicon oxide based material, there have been the problematical offsetting effects of reduced mechanical strength of the IMD layer as well as adhesion to underlying and/or overlying layers such as etch stop layers. The problem of reduced mechanical strength and adhesion can manifest itself in many ways including delamination during subsequent processing steps such as CMP which exerts a delaminating mechanical force or during chip packaging operations where chip molding material can cause thermal mismatch stresses leading to delamination of a chip. In addition, device layer formation in multi-level devices results in an accumulation of mechanical stresses as device layers are sequentially formed which can contribute to lower critical delamination stress.
It would therefore be advantageous to develop an improved structure and method for preventing delamination of multi-level integrated circuit devices including improved adhesion strength between material layers as well as reducing mechanical and thermal mismatch stresses in chips and in chip packaging operations.
It is therefore an object of the invention to provide an improved structure and method for preventing delamination of multi-level integrated circuit devices including improved adhesion strength between material layers as well as reducing mechanical and thermal mismatch stresses in chips and in chip packaging operations, as well as overcoming other shortcomings of the prior art.